? semiconductor components industries, llc, 2006 march, 2006 ? rev. 4 1 publication order number: NTP52N10/d NTP52N10 power mosfet 60 amps, 100 volts n ? channel enhancement mode to ? 220 features ? source ? to ? drain diode recovery time comparable to a discrete fast recovery diode ? avalanche energy specified ? i dss and r ds(on) specified at elevated temperature ? pb ? free package is available* applications ? pwm motor controls ? power supplies ? converters maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit drain ? to ? source voltage v dss 100 vdc drain ? to ? source voltage (r gs = 1.0 m ) v dgr 100 vdc gate ? to ? source voltage ? continuous ? non ? repetitive (t p 10 ms) v gs v gsm 20 40 vdc drain ? continuous @ t a 25 c ? continuous @ t a 100 c ? pulsed (note 1.) i d i d i dm 60 40 156 adc total power dissipation @ t a 25 c derate above 25 c p d 214 1.43 watts w/ c operating and storage temperature range t j , t stg ? 55 to +175 c single drain ? to ? source avalanche energy ? starting t j = 25 c (v dd = 50 v, v gs = 10 vdc, i l (pk) = 40 a, l = 1.0 mh, r g = 25 ) e as 800 mj thermal resistance ? junction ? to ? case ? junction ? to ? ambient r jc r ja 0.7 62.5 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. pulse test: pulse width = 10 s, duty cycle = 2%. *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 60 amperes 100 volts 30 m @ v gs = 10 v to ? 220 case 221a style 5 1 2 3 4 n ? channel d s g marking diagram & pin assignment NTP52N10g ayww d http://onsemi.com s d g a = assembly location y = year ww = work week g = pb ? free package device package shipping ordering information NTP52N10 to ? 220 50 units / rail NTP52N10g to ? 220 (pb ? free) 50 units / rail 1
NTP52N10 http://onsemi.com 2 electrical characteristics (t c = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain ? to ? source breakdown voltage (v gs = 0 vdc, i d = 250 adc) temperature coefficient (positive) v (br)dss 100 ? ? 160 ? ? vdc mv/ c zero gate voltage drain current (v gs = 0 vdc, v ds = 100 vdc, t j =25 c) (v gs = 0 vdc, v ds = 100 vdc, t j =125 c) i dss ? ? ? ? 5.0 50 adc gate ? body leakage current (v gs = 20 vdc, v ds = 0 vdc) i gss ? ? 100 nadc on characteristics gate threshold voltage (v ds = v gs , i d = 250 adc) temperature coefficient (negative) v gs(th) 2.0 ? 2.92 ? 8.75 4.0 ? vdc mv/ c static drain ? to ? source on ? state resistance (v gs = 10 vdc, i d = 26 adc) (v gs = 10 vdc, i d = 26 adc, t j = 125 c) r ds(on) ? ? 0.023 0.050 0.030 0.060 drain ? to ? source on ? voltage (v gs = 10 vdc, i d = 52 adc) v ds(on) ? 1.25 1.45 vdc forward transconductance (v ds = 26 vdc, i d = 10 adc) g fs ? 31 ? mhos dynamic characteristics input capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz) c iss ? 2250 3150 pf output capacitance c oss ? 620 860 transfer capacitance c rss ? 135 265 switching characteristics (notes 2. & 3.) turn ? on delay time (v dd = 80 vdc, i d = 52 adc, v gs = 10 vdc, r g = 9.1 ) t d(on) ? 15 25 ns rise time t r ? 95 180 turn ? off delay time t d(off) ? 74 150 fall time t f ? 100 190 gate charge (v ds = 80 vdc, i d = 52 adc, v gs = 10 vdc) q tot ? 72 135 nc q gs ? 13 ? q gd ? 37 ? body ? drain diode ratings (note 2.) diode forward on ? voltage (i s = 52 adc, v gs = 0 vdc) (i s = 52 adc, v gs = 0 vdc, t j = 125 c) v sd ? ? 1.06 0.95 1.5 ? vdc reverse recovery time (i s = 52 adc, v gs = 0 vdc, di s /dt = 100 a/ s) t rr ? 148 ? ns t a ? 106 ? t b ? 42 ? reverse recovery stored charge q rr ? 0.66 ? c 2. indicates pulse test: p.w. = 300 s max, duty cycle = 2%. 3. switching characteristics are independent of operating junction temperature.
NTP52N10 http://onsemi.com 3 t j = ? 55 c t j = 100 c 100 10 1000 10000 60 40 80 20 0 100 0 60 23 1 i d , drain current (amps) 0 v gs , gate ? to ? source voltage (volts) figure 1. on ? region characteristics figure 2. transfer characteristics i d , drain current (amps) 10 0.01 30 0 20 40 50 100 figure 3. on ? resistance versus drain current and temperature i d , drain current (amps) figure 4. on ? resistance versus drain current and gate voltage i d , drain current (amps) r ds(on) , drain ? to ? source resistance ( ) figure 5. on ? resistance variation with temperature t j , junction temperature ( c) figure 6. drain ? to ? source leakage current versus voltage v ds , drain ? to ? source voltage (volts) i dss , leakage (na) 100 ? 50 100 50 0 ? 25 175 23 6 30 70 60 50 40 100 v ds , drain ? to ? source voltage (volts) 20 40 80 10 v gs = 0 v t j = 150 c t j = 100 c i d = 26 a v gs = 10 v v gs = 10 v v ds 10 v t j = 25 c v gs = 10 v r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance (normalized) 9 v 6 v 25 45 467 5 8 v 5.5 v 5 v 8 7 80 0.02 0.03 0.04 0.05 t j = ? 55 c t j = 100 c t j = 25 c 0 0.01 20 40 60 100 80 0.02 0.03 0.04 0.05 t j = 25 c 125 0.5 1 1.5 2 2.5 80 0 89 t j = 25 c 7 v 4.5 v 4 v 60 70 90 v gs = 10 v v gs = 15 v 90 75 150 0
NTP52N10 http://onsemi.com 4 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because drain ? gate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg ? v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turn ? on and turn ? off delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg ? v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the off ? state condition when calculating t d(on) and is read at a voltage corresponding to the on ? state when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. 3000 0 6000 1000 2000 4000 10 5 0 25 10 515 gate ? to ? source or drain ? to ? source voltage (volts) figure 7. capacitance variation v gs v ds v gs = 0 v v ds = 0 v t j = 25 c c rss c iss c oss c rss c iss c, capacitance (pf) 5000 20
NTP52N10 http://onsemi.com 5 r g , gate resistance (ohms) 1 10 100 1000 10 t, time (ns) v dd = 80 v i d = 52 a v gs = 10 v 100 t r t d(off) t d(on) t f 1 v gs , gate ? to ? source voltage (volts) 60 0 0.95 0.25 drain ? to ? source diode characteristics v sd , source ? to ? drain voltage (volts) figure 8. gate ? to ? source and drain ? to ? source voltage versus total charge figure 9. resistive switching time variation versus gate resistance v gs = 0 v t j = 25 c figure 10. diode forward voltage versus current 100 80 60 40 20 0 10 6 2 0 q g , total gate charge (nc) 20 8 4 20 70 40 0 10 50 30 60 0.35 0.45 0.55 0.65 0.75 0.85 20 40 50 10 30 i d = 52 a t j = 25 c v gs q 2 q 1 q t v ds 12 14 16 18 v ds , drain ? to ? source voltage (volts) i s , source current (amps) safe operating area the forward biased safe operating area curves define the maximum simultaneous drain ? to ? source voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, ?transient thermal resistance ? general data and its use.? switching between the off ? state and the on ? state may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r ,t f ) do not exceed 10 s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) ? t c )/(r jc ). a power mosfet designated e ? fet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases non ? linearly with an increase of peak current in avalanche and peak junction temperature. although many e ? fets can withstand the stress of drain ? to ? source avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature as shown
NTP52N10 http://onsemi.com 6 in the accompanying graph (figure 12). maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated. safe operating area r(t). effective transient thermal resistance (normalized) e as , single pulse drain ? to ? source avalanche energy (mj) i d , drain current (amps) figure 11. maximum rated forward biased safe operating area t, time ( s) 0.1 1.0 0.01 0.1 0.2 0.02 d = 0.5 0.05 0.01 single pulse r jc (t) = r(t) r jc d curves apply for power pulse train shown read time at t 1 t j(pk) ? t c = p (pk) r jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 1.0 10 0.1 0.01 0.001 0.0001 0.00001 t j , starting junction temperature ( c) figure 12. maximum avalanche energy versus starting junction temperature 0.1 1 100 v ds , drain ? to ? source voltage (volts) figure 13. thermal response 1 1000 r ds(on) limit thermal limit package limit 0.1 0 25 50 75 100 125 200 i d = 40 a 10 10 150 figure 14. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b 100 500 400 300 800 1000 100 v gs = 20 v single pulse t c = 25 c 600 1 ms 100 s 10 ms dc 10 s 700
NTP52N10 http://onsemi.com 7 package dimensions to ? 220 case 221a ? 09 issue aa notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension z defines a zone where all body and lead irregularities are allowed. dim min max min max millimeters inches a 0.570 0.620 14.48 15.75 b 0.380 0.405 9.66 10.28 c 0.160 0.190 4.07 4.82 d 0.025 0.035 0.64 0.88 f 0.142 0.147 3.61 3.73 g 0.095 0.105 2.42 2.66 h 0.110 0.155 2.80 3.93 j 0.018 0.025 0.46 0.64 k 0.500 0.562 12.70 14.27 l 0.045 0.060 1.15 1.52 n 0.190 0.210 4.83 5.33 q 0.100 0.120 2.54 3.04 r 0.080 0.110 2.04 2.79 s 0.045 0.055 1.15 1.39 t 0.235 0.255 5.97 6.47 u 0.000 0.050 0.00 1.27 v 0.045 ??? 1.15 ??? z ??? 0.080 ??? 2.04 b q h z l v g n a k f 123 4 d seating plane ? t ? c s t u r j style 5: pin 1. gate 2. drain 3. source 4. drain on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?t ypicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license un der its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended f or surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in a ny manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 NTP52N10/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082 ? 1312 usa phone : 480 ? 829 ? 7710 or 800 ? 344 ? 3860 toll free usa/canada fax : 480 ? 829 ? 7709 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
|
